A novel path delay fault simulator using binary logic

A novel path delay fault simulator for combinational logic circuits which is capable of detecting both robust and nonrobust paths is presented. Particular emphasis has been given for the use of binary logic rather than the multiple-valued logic as used in the existing simulators which contributes to the reduction of the overall complexity of the algorithm. A rule based approach has been developed which identifies all robust and nonrobust paths tested by a two-pattern test <V1,V2>, while backtracing from the POs to PIs in a depth-first manner. Rules are also given to find probable glitches and to determine how they propagate through the circuit, which enables the identification of nonrobust paths. Experimental results on several ISCAS'85 benchmark circuits demonstrate the efficiency of the algorithm

A Genetic Algorithm-Based Circuit Partitioner For Mcms

Multichip Modules (MCMs) is a packaging technology gaining importance, because it reduces the interconnect delays across chips, by bringing the interconnect delays closer in magnitude to the on-chip delays, The problem here is to partition a circuit across multiple chips, producing MCMs. Partitioning is a combinatorial optimization problem. One of the methods to solve the problem is by the use of Genetic Algorithms (GAs), which are based on genetics. GAs can be used to solve both combinatorial as well as functional optimization problems. This paper solves the problem of partitioning using the GA approach. The performance of GAs is compared with that of Simulated Annealing (SA), by executing the algorithms on three benchmark circuits. The effect of varying the parameters of the algorithm on the performance of GAs is studied

An efficient automatic test generation system for path delay faults in combinational circuits

The new test pattern generation system for path delay faults in combinational logic circuits considers robust and nonrobust tests, simultaneously. Once a robust test is ob-tained for a path with a given transition, another test for the same path with the opposite transition is immediately derived with a small extra effort. To facilitate the simul-taneous consideration of robust and nonro.bust tests, we derive a new nine-value logac system. An efficient multi-ple backtrace procedure satis,Ees test generation objectives. We also use a path selection method which covers all lines in the logic circuit by the longest and the shortest possible paths through them. A fault simulator in the system gives information on robust and nonrobust detection of faults either from a given target set or all path faults. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits substantiate the eficiency of our algorithm in comparison to other published results

Line coverage of path delay faults

We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition,but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus,the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits

On Test Coverage of Path Delay Faults

We propose a coverage metric and a two-pass test gen-eration method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and a falling transition. However, the test criterion is different from that of the slow-to-rise and slow-to-fall transition faults. The test, called “line delay test”, as a path delay test for the longest sensitizable path produc-ing a given transition on the target line. The maximum number of tests (and faults) is limited to twice the num-ber of lines. However, the line delay test criterion resem-bles path delay test and not the gate or transition delay test. Using a two-pass test generation procedure, we begin with a minimal set of longest paths covering all lines and generate tests for them. Fault simulation is used to de-termine the coverage metric. For uncovered lines, an the second pass, several paths of decreasing length are tar-geted. We present a theorem stating that a redundant stuck-at fault makes all path delay faults involving the faulty line untestable for either a rising or falling transi-tion depending on the type of the stuck-at fault. The use of this theorem considerably reduces the effort of delay test generation. We give results on benchmark circuits.